Arasan MIPI PHY’s are readily available and in production with multiple foundries from 16nm to 180nm. Our PHY’s are designed for low power on the most advanced nodes for the mobile market while also targeting the automobile market on specialized nodes where extreme temperature tolerance is required.
MIPI C-PHY – physical interface for CSI-2 and DSI-2 providing 5.7Gbps per lane of bandwidth The MIPI C-PHY V1.0 improves throughput over a bandwidth-limited channel, allowing more data without increased signaling clock. It is intended to be used for camera interface (CSI-2 v1.3) and display interface (DSI-2 v1.0). The signaling interface uses a 3-phase transceiver that encodes 3-bit symbols over 3 wires. This is different from the two-wire differential “lane” used in D-PHY.
MIPI D-PHY – physical interface for CSI-2, DSI, and DSI-2 providing 2.5Gbps per lane of bandwidth Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital (PPI) interface to control the I/O functions.
MIPI M-PHY – physical interface for UFS, providing up to 5.9Gbps of bandwidth Arasan’s M-PHYs are of Type 1, which apply to UFS protocols. The Multi-gear M-PHY 3.0 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.