Arasan’s 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between AHB/AXI Bus and the 10 Gigabit Media Independent Interface (XGMII) using a powerful 64-bit Scatter Gather DMA.
The 10 Gigabit Ethernet IP core is designed for applications such as integrated networking devices, host bus adapters, PCI-Express Ethernet controllers, and Ethernet adapter cards.
The XGMAC operates at a speed of 10 Gbps in full duplex mode only. The XGMAC provides features that include transmit and receive message data encapsulation, framing, error code detection, dynamic FCS generation and calculation on frame by frame basis, automatic pad insertion and deletion to enforce minimum frame size requirements. The 10 Gigabit Ethernet XGMAC also supports flow control operation by supporting generation and decoding of PAUSE control frames and supports generation of Management frames on MDC/MDIO signals to communicate with an external PHY device.
AHB/AXI Interface and Scatter/Gather DMA
The XGMAC IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. An AHB/AXI master and a 64-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance. The XGMAC core supports the XGMII interface and a MDIO/MDC (Management Data Input/ Output and Management Data Clock) management interface provides control and management functions to external PHY devices.
The 10 Gigabit Ethernet XGMAC IP also provides enhanced programmable features for minimizing applications complexity and pre/post message processing. The XGMAC IP supports MIB, SNMP, RMON, VLAN Q-Tag frame, and Jumbo frames. It also includes dynamic generation, checking, and stripping of FCS field, and automatic pad field insertion.
Other features of the XGMAC IP include generation and decoding of PAUSE control frames, frame boundary delimitation, frame synchronization, and error detection. See the Feature tab below for a full list of features.
10 Gbps data transfer rates.
Operates at Independent Transmit and Receive 156.25 MHz Clocks as defined in the Clause 46 of the IEEE 802.3-2008 Specification.
Option to operate at Independent Transmit and Receive 161.13 MHz Clock when interfacing with the XG-64B66B PCS Module.
Direct Connection to either 64-bit or 128-bit AHB or AXI Interface Master Interface and 32-bit AHB or AXI Target Interface
Independent 64-bit or 128-bit scatter-gather DMA for Transmit and Receive operations.
IEEE 802.3-2008 compliant XGMII interface (Clause46) to talk to an external PHY.
Optional demultiplexed XGMII Interface with 64-bit data and 8-bit control to interface to XG-XAUI or XG-64B66B PCS Modules
Optional VLAN Q-Tag frame Support.
Full-Duplex mode of operation while supporting PAUSE frame based Flow Control.
Generation of Clause22 (Direct) or Clause45 (Indirect) Compliant Management frames under software control on MDC/MDIO interface to talk to external PHY device.
802.3 Compliant MIB, SNMP, RMON management support by using variety of 48-bit counters.
Configurable Transmit and Receive FIFO‟s.
Support‟s Jumbo Frames during both transmit and receive operations.
Optional Power Management Support by supporting Magic Packet and Wake-Up Frame‟s.
AMBA Compliant AHB or AXI Interface (XGMAC-AHB or XGMAC-AXI)
Bus Mastering using AHB or AXI Master Interface to transfer packets between the Host memory and the Internal FIFO‟s and to fetch descriptors from the Host memory.
The AHB or AXI Master Interface supports either 64-bit data transfers or 128-bit data transfers, based on DMA operating in 64-bit or 128-bit mode.
AHB or AXI Target(Slave) Interface to program/control the operation and program the Registers inside the Core using a 32-bit interface.
64-bit or 128-bit scatter-gather DMA, Independent for Transmit and Receive Operations.
Independent Transmit and Receive Operation.
The Transmit and Receive DMA can be configured to perform transfers in either 64-bit mode (data bus width is 64-bit wide) or 128-bit mode (data bus width is 128-bit wide).
Either Linked-list or Ring (Chained) Descriptors.
Programmable Skip length between the Descriptors in case of Chained Descriptors.
Up to two buffers per Descriptor
Programmable Buffer Size (up to 1K bytes) configurable for every descriptor.
Programmable Burst Size for efficient Host Bus utilization.
Buffer Alignment Support at Byte Level for both transmit and receive buffers.
Flexible Transmit/Receive Arbitration.
XGMAC Functional Specification Version: 1.02
Programmable Interrupt Structure.
Big/Little Endian operation for both Data buffers and Descriptors structure.
Variable length (96 BT, 128 BT, 256 BT) Inter Frame Gap (IFG) on back to back frame transmission, with default value of 96 Bit Times of IFG.
Deficit IDLE Counter to maintain an average IFG of 96 bit times.
Automatic generation of FCS during transmission.
Automatic generation of PAD during transmission to meet the Ethernet MinFrameSize requirement.
Option to disable PAD and/or CRC32 insertion on transmission on a per frame basis.
Preamble detection and stripping on reception. Checks for proper START and SFD byte lane alignment.
Handles minimum IFG of 5 Bytes during back to back frame reception.
Flexible Address filtering modes.
Four 48-bit MAC Addresses for Perfect Address match with individual address enable/disable.
Inverse Address filtering enable on the above four 48-bit MAC addresses.
64-bit Hash table to filter multicast addresses.
Promiscuous mode of operation.
Reception of broadcast frames.
Automatic checking of the FCS field for correct CRC value.
Automatic checking of Runt frames and option to filter them out from the Application.
Automatic checking of the DATA field length in case of 802.3 type frames with length field.
Configurable field to detect MaxFrameLen frames.
Automatic adjustment to the MaxFrameLen field for VLAN Tagged frames.
Detection of Receive Error indication on XGMII interface during Frame reception.
Comprehensive 32-bit Status information provided on each receive frame.
Flow Control Functions
Software controlled PAUSE control frame generation with programmable pause quanta.
Option to generate PAUSE control frames on FIFO Almost-Full and FIFO Almost-Empty conditions (under controls from Application).
Option to use reserved multicast address or programmed unicast address in the DA field of the PAUSE Control frame.
Generation of the PAUSE control frame even when the Transmit logic is in pause mode.
Automatic detection of PAUSE frames with DA field of either the reserved multicast address or the unicast MAC Address(s) of the device.
Checking for valid OPCODE, frame size, and FCS field in the PAUSE Control frames.
Disabling of the Transmitter for the length of time mentioned in the pause quanta field in the received PAUSE Frame.
Option to block the PAUSE frames received from transferring to Application.
RMM Compliant Synthesizable RTL design in Verilog
Easy-to-use test environment
Fully IEEE 802.3-2008 compliant core
Premier direct support from Arasan IP core designers