The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Media Independent Interface (GMII). It also supports optional Reduced MII (RGMII), and Serial GMII (SGMII). The Gigabit Ethernet core is designed for SoC and mobile applications such as integrated networking devices, PCI-Express Ethernet controllers, and Ethernet adapter cards. The Gigabit Ethernet Core IP supports half-duplex mode at 10/100 Mbps and full-duplex mode at 10/100/1000 Mbps.
The Gigabit Ethernet MAC IP core consists of two configurable FIFOs on both transmit and receive sides to handle the application’s latency during frame transmission and reception. A processor bus master and 32-bit scatter-gather DMA transfer packets between the internal FIFOs and the host memory to enhance system performance
IEEE 802.3 Compliant Core
The Arasan Gigabit Ethernet MAC – Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard. The Gigabit Ethernet core supports 4-bit MII based 10/100 Mbps PHY and 8-bit GMII based 10/100/1000 Mbps PHY. A MDIO/MDC (Management Data Input/Output and Management Data Clock) management interface provides control and management functions to external PHY devices.