xSPI PSRAM x16 Master IP core | Arasan Chip Systems

Arasan Chip System’s Sureboot™ 16-bit xSPI PSRAM IP master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. This IP is specifically engineered to support AP Memory’s Xccela™ PSRAM and their latest LVpSRAM™, providing a high-performance, low-power memory interface for next-generation

16-bit xSPI PSRAM IP is a high-performance memory interface designed for maximum speed and flexibility, doubling standard throughput by using two 8-bit data lanes to transfer 32 bits every 266MHz clock cycle and supports 1.2v and 1.8v devices. It is fully compliant with the JEDEC JESD251C specification and backward compatible with Octal, Quad, and Dual SPI standards, ensuring it works with both modern and legacy devices. The IP simplifies system integration by booting directly into SPI mode for immediate memory access and features AXI memory mapping with built-in DMA support.

Features

• JESD 251 compliant

Protocols 1 & 2

• Support HyperRAM^TM, HyperFLASH^TM, xCella^TM, LVpSRAM™ and xSPI

• AP Memory^TM 8-bit and 16-bit PSRAM support

• Supports two 8b data lanes

Doubles throughput (up to 1GB/s)
Works with both 16b and non-16b memories

• Multi SPI support

Octal, Quad, Dual SPI
DDR/DTR support
Resets into SPI mode
24 or 32b addressing
User selectable cmds
XIP read support
DS support in all modes

• Full R/W support

• AXI Memory Mapped

Parameterized width
Full & Narrow burst
Max Bus Throughput
Native WRAP support

• AXI DMA master

High Speed Bulk ops
Parameterized width
Full & Narrow burst
Max Bus Throughput

• AXI4-Lite Conﬁg Port

Low level cmd access
Conﬁgurable R/W cmds

• Conﬁgurable clocking

Device clock
Integer clock divider
Separate AXI clock
(Optional) Clock gating

• JESD SFDP capable