Demand for mobile content capacity and bandwidth for video, pictures and music is ever increasing. To address this demand in the next generation of smartphones, tablets, and portable devices, the eMMC 5.1 Specification from JEDEC, improves the current HS400 speeds operating at 3.2Gbps, with “command queuing” – making the data transfers highly efficient by offloading the software overhead into the controller. eMMC 5.1 further improves the reliability of operation by utilizing an “enhanced strobe” at the PHY layer. The eMMC5.1 is backward compatible with the existing eMMC 4.51 and eMMC 5.0 Devices.
Arasan’s 28nm and 16nm general purpose I/O PADs are multipurpose PADs that can be programmed to operate in different modes: 1) Output with predetermined source/sink impedance, 2) Open drain, 3) Input, 4)Tristate and 5) Weak pull up or pull down. The I/O PADs are specially designed to seamlessly integrate with Arasan’s eMMC 5.1 and eMMC 5.0 host controller IP. Arasan introduced the industry’s first HS400PHY in 2013 on multiple 28nm nodes which are now in production. Development of the eMMC PHY in 16nm was completed during early 2014 and is also now production ready. Arasan is currently developing HS400 in 14nm and will be made available as part of it’s Total eMMC 5.1 IP Solution.
