Arasan has a diverse portfolio of connectivity IP products including SPI, I2C, I2S, and UART. These protocols are vital for the integration of SoCs with peripheral chipsets in order to form a complete hardware platform. They are frequently used by the SoC to configure, control and gather diagnostic information at the platform level to ensure the correct operation of the hardware. Arasan’s proven Connectivity IP Solutions provides a risk-free path to integrating these interfaces in SoC designs:
High quality IP cores ensure inter-operability between SoCs and peripherals
In-house domain expertise ensures high-quality support throughout the SoC development cycle
Total IP solution includes RTL source code, synthesis scripts, test environment, and documentation
The Arasan I2S Controller IP Core is a two-channel I2S serial audio controller compliant to the Philips* Inter-IC Sound specification. The I2S bus is used for connecting audio components such as speakers, DACs, or audio subsystems.
The Arasan I2S Controller IP Core provides a 32-bit parallel processor bus as the application interface. The controller’s I2S interface consists of one transmitter and one receiver. Each channel can be programmed as an I2S master or an I2S slave. The Bit Clock (BLCK) and Left and Right Clock (LRCK) provide synchronization for the transmit and receive data. The I2S Controller IP supports 44.1KHz audio samplingrates. DAC/ADC resolution is configurable from 8-bit to 32-bit. The included transmit FIFO and receive FIFO handle data transfers between the I2S interface and application interface. These two interfaces can be operated in two independent clock domains. The I2S Controller also includes interrupt support for reporting FIFO and other conditions. The I2S Controller IP supports a 32-bit parallel bus interface. AHB, PCI or other custom specific buses can also be provided upon request.
The SPI – AHB bridge enables an AHB host to access a serial device at high-speed through the SPI interface. The controller can be used in applications such as flash memory card and digital camera. Both AHB and SPI support master and slave modes. The AHB – SPI bridge performs either parallel-to-serial conversion or serial-to-parallel conversion with a maximum throughput of 50 Mbit/sec. A 32-bit x 32-bit transmit FIFO and a 32- bit x 32-bit receive FIFO serve as the data buffer to coordinate data flows between the AHB and SPI interfaces. The AHB master consists of a DMA controller to enhance the system performance. A SPI Clock Generator is included to provide adjustable input clock to the SPI controller. A SPI clock frequency from 500 KHz to 50 MHz can be selected. The Status and Interrupt Generator provides data transaction information to the AHB host processor that reflects the FIFOs and DMA states. The SPI controller consists of one SPI master and one SPI slave and it can be programmed by an AHB host to support the TI, Motorola, or National SPI protocol. Full SPI duplex mode is supported. The Arasan High Speed SPI – AHB IP Core is an RTL design in Verilog that implements an SPI – AHB controller on an ASIC, or FPGA. The Arasan High Speed SPI – AHB IP Core has been widely used in different applications by major chip vendors.
The synchronous I2C interface is a block that interconnects an APB bus. The APB – I2C Bridge interfaces to the APB bus on the system side and the I2C bus. The APB interface is used to easily integrate the Bridge Controller for any SOC implementation. The APB – I2C is a master/slave interface that enables synchronous serial communication with the other master or slave I2C peripherals having I2C compatible interface. The controller performs the following functions:
Parallel-to-serial conversion on data written to an internal 8bit wide, 1024 deep FIFO.
serial-to-parallel conversion on received data, buffering it in a similar 8-bit wide, 1024 deep FIFO
The Arasan 16550D High Speed UART IP core is a16550-compliant Universal Asynchronous Receiver/Transmitter (UART) with FIFO or expanded FIFO. UART complies to the standard 16550D with FIFOs. The UART performs serial to parallel conversion of the data received from the external device and parallel to serial conversion of data received from the AHB bus Interface. It supports both character and FIFO modes. The complete status of the UART can be read from its registers