ONFI 4.2 NAND Flash Controller
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and innovative IP solutions are needed to keep pace. NAND Flash is being incorporated into all types of products including Portable memory drives, Media players, Digital cameras, Smartphones, eBook Readers, Tablets, Digital TVs, Digital camcorders, PCs, and so on. Arasan is in the perfect position to give you what you need.
The Arasan NAND Flash Controller IP Core is a full-featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA development. Designed to support SLC, MLC and TLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable NAND Flash memory device up to 1024Gb from leading memory providers – Micron, Samsung, Toshiba and Hynix. The IP core includes a host of configuration options from page size to bank selects. The controller offers Hamming Code (1-Bit error correction and 2-Bit error detection) and BCH (option for 4-, 8-, 12-, up to 32-Bit error correction) Error Code Correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash.
The IP core supports the Open NAND Flash Interface Working Group (ONFI) 3.2, 4.0, 4.1 and 4.2 standards. It can also support a variety of host bus interfaces for easy adoption into any design architecture – AXI, AHB, APB, OCP, 8051 or custom buses. The slave AXI IP supports an external DMA interface where the master AXI incorporates an internal DMA controller.
The Arasan NAND Flash Controller IP Cores are delivered in Verilog RTL that can be implemented in an ASIC or FPGA. They are fully tested with vendor models and hardware is tested with FPGA’s. The core includes RTL code, test scripts and a test environment for complete simulation and verification.
NAND Flash Interface
Arasan Chip System’s NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash Interface (ONFI) Specification, version 4.2 dated February, 2020. It is backwards compatible, support- ing the Single Data Rate (asynchronous) mode, as well as the newer Double Data Rate (NVDDR) modes such as NVDDR2 and NVDDR3. All posted rates for these various modes are also supported, from the NVDDR 33MHz mode at the low end all the way up to the newer 800MHz (1.6GT/s) I/O speeds.
The IP consists of two primary components: a host controller and a high speed PHY. The host controller is controlled via an AXI slave port. A scatter/gather DMA provides a separate AXI master port, allowing for extended unattended reads or writes. The host controller supports either AXI3 or AXI4, and a user configurable data path width.
AXI Control Interface
The primary interface to host controller is a memory mapped AXI slave port. This interface can be used to issue commands directly to the flash, to program the DMA, or to manually trigger data copies from a local SRAM to the flash or from the flash to the local SRAM.
One section of the memory mapped AXI slave port allows high speed access to this external SRAM. This SRAM is used to store read results, or buffer write data so that the IP can operate at high speed.
