Arasan’s MIPI® D-PHY compliant to the MIPI D-PHY Specification v2.1 supports:
This specification is primarily intended to define a solution for a bit-data rate range of:
- 80 to 1500 Mbps per Lane without de-skew calibration
- up to 2500 Mbps with de-skew calibration,
- up to 4500 Mbps with equalization.
When the DUT implementation supports a data rate greater than 1500 Mbps, it shall also support de-skew capability. When a PHY implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available.
Arasan D-PHY IP Core is seamlessly integrated with Arasan’s MIPI CSI IP and DSI IP Controller Cores.
Arasan offers industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY. The MIPI D-PHY IP is available in foundry processes spanning 7nm to 180nm. Arasan specializes in porting Analog Transceiver IP Cores to new foundry processes.
Arasan’s MIPI® D-PHY IP Core is fully compliant to the D-PHY specification version 2.1. It provides a point to point connection between master and slave or host and device that comply with a relevant MIPI®