Overview
Arasan’s SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together. This SWI3S Peripheral IP is a responsive, time-synchronized, and power-aware component within the SoundSire-I3S ecosystem.
SWI3S Specifications Support
• Implements & supports MIPI SoundWire-I3S Specification
Core Functional Features
• Capable of receiving timing information from Manager to
– Send and receive data bits
– Generate audio sampling events• Capable of Transport audio sample streams typically via
– Multiple channels
– PDM or PCM formats
– Supports various sample rates- 44.1KHz, 48KHz
– Support for Flow-Controlled transmission (sink-and-source-controlled)
– Low-Latency transmission design (~300ns)
Control and Communication Features
• Allows Manager’s commands for the peripheral registers
• Read Status Information and communicates Interrupts
• Supports In-band signaling like wake-up requests, Interrupt conditions, and reset signaling
Power and System Management
• Support for link-power states like sleep, wake and clock pause
• Support for request link control actions like link awake and cold boot
Protocol and Error Handling
• Support for peripheral response states for reads, writes and commits including WRITE-OK, READ-DATA-NOW, COMIT-READY etc.
• Support handling of transport protocol errors through error counters and interrupt mechanisms for the Manager
Includes
• System Verilog RTL Source Code
• A simplified Testbench with simulation models to run initial set of tests after release
• Lint Report
• Synthesizable Netlist
• Synthesis Scripts and exception lists
• Timing Report
• Protocol Compliance & Coverage Report
• Sample Firmware with Drivers
• Application Notes
