The C/D-PHY HDK is build using Arasan’s TSMC 12nm Fin-FET C/D-PHY ASIC. Future generations of the HDK will use Arasan’s TSMC 7nm Fin-FET C/D-PHY ASIC.
The HDK supports C-PHY v2.0 with speeds up to 6 Gsps per trio & D-PHY v2.5 with speeds up to 6 Gbps per lane. This HDK enables customers to prototype their C/D-PHY based projects using Arasan’s MIPI CSI-2 or DSI-2 IP controller cores and software stacks.
Host and Device components are connected by a serial link employing the MIPI® Alliance C/D-PHY standard.
This platform is used for Functional Testing
- CSI-2/DSI-2 -Tx to CSI-2/DSI-2 -Rx Video transfers
- Static images
- Motion Video
- 1/2/3 Lane traffic
and MIPI – CSI-2/DSI-2 Protocol Testing
- Using 3rd party MIPI traffic generators
- Agilent Protocol Tester/Analyzer.
- Moving pixel Protocol Tester.
