The C-PHY HDK is build using Arasan’s TSMC 28nm C-PHY ASIC. Future generations of the HDK will use Arasan’s TSMC 12nm C-PHY ASIC.
The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz. This HDK enables customers to prototype their CPHY based projects using Arasan’s MIPI CSI or DSI IP controller cores and software stacks.
Host and Device components are connected by a serial link employing the MIPI® Alliance CPHY standard.
This platform is used for Functional Testing
- CSI/DSI-Tx to CSI/DSI-Rx Video transfers
- Static images
- Motion Video
- 1/2/3 Lane traffic
and MIPI – CSI/DSI Protocol Testing
- Using 3rd party MIPI traffic generators
- Agilent Protocol Tester/Analyzer.
- Moving pixel Protocol Tester.
