MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) on the other chip via a serial interconnect that consists of two differential lines. The differential lines can carry both High-Speed (HS) and Low-Speed (LS) signals.
Arasan’s M-PHYs are of Type 1, which apply to UFS, LLI and CSI-3 protocols. The Multi-gear M-PHY 3.0 consists of analog transceivers, high speed PLL, data recovery units as well as the state-machine control — all in a single GDSII. The interface to the link protocol-specific controller (host or device) is compliant to the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
Design philosophy: Arasan’s approach to M-PHY design is end-to-end protocol specific. Different protocols have different requirements in terms of clocking. A single version of M-PHY 3.1 that caters to all protocols can become prohibitively large and consume more power than necessary. Hence Arasan delivers the most area and power efficient implementation for each MIPI M-PHY 3.1 protocol.
Arasan follows a rigorous practice of co-verifying the controllers and their corresponding PHY’s to ensure that they operate together as intended. These, together with Arasan’s software stacks, are mapped onto Arasan’s Hardware Validation Platforms, which are used for early compatibility and interoperability testing with the corresponding host/device platforms from Arasan and a number of MIPI contributor members. This minimizes end-to-end compatibility risk for customers.