Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE standard v2.0. The MIPI RFFE bus is a 2-wire serial interface that utilizes a bus frequency of up to 26 MHz and timing accurate trigger mechanisms to allow control of timing-critical functions. It is used to connect a digital RFIC to RF front end components, like Power Amplifiers, Low-Noise Amplifiers, and Antenna Sensors, which are considered RFFE Slaves.
A number of new features were introduced in RFFEv2 including
- Multi-Master support
- Interrupt Capable Slaves functionality
- Extended Frequencies
- Synchronous Reads
- Definitions for new Reserved Registers.
One key component of RFFEv2 was to retain backward-compatibility, especially for RFFEv1 Slave devices. This requirement enables RFFEv1 Slave devices to function properly in an RFFEv2 system. Of course, such RFFEv1-compliant Slave devices in an RFFEv2 system are limited to their RFFEv1 functionality.
As a minimum an RFFE-compatible Slave device must implement the following four features:
- Internal generation of a POR (power-on-reset) using detection of VIO assertion
- SSC detection
- Support for at least one RFFE CS (if only one is supported it must be a Write operation)
- Support for Master writes to the PWR_MODE bits in PM_TRIG Register
The RFFE Slave IP core typically resides in the RFIC in a mobile platform, and utilizes the RFFE bus to identify, program, and monitor the registers in RF front end Slave devices through programmed IO. It is designed to support existing standards such as LTE, UMTS, HSPA and EGPRS, and is usable in configurations ranging from single Master/single Slave to multi-Master/multi-Slave.
The RFFE Slave V2.0 IP Core resides in each RF front end component. At a minimum, Arasan delivers RFFE Slave in RTL form. Physical designs of the complete RFFE Slave, including the Pad Logic block for CLK and DATA as shown below, can be provided upon request