The Arasan MIPI CSI-2 Transmitter IP Core functions as a MIPI Camera Serial Interface between a peripheral device (display module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Transmitter IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
Pixel Data received from over the Camera Sensor Bus is packed into bytes by the Transmitter IP. The packing of the pixel into bytes follows the CSI-2 spec and based on the pixel format support. This IP calculates and appends an ECC/CRC value to a short packet (or) to the header of a long packet. Selection of ECC/CRC to the header is done based on the PHY connected. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends to the packet as a Packet Footer (PF). The packet is buffered in a FIFO and sent to one or more D-PHY/C-PHY depending on the lane distribution scheme set by the camera sensor/user.
CSI-2 RX v1.2 is compliant to MIPI CSI-2 specification v1.2 and supports D-PHY v1.1.
CSI-2 RX v1.3 is compliant to MIPI CSI-2 specification v1.3 and supports DPHY v1.2 and the new MIPI C-PHY v1.1.
Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.
The Datasheet for CSI-2 RX v1.3 is available on request