Arasan’s xSPI/PSRAM interface PHY is designed to work with both the xSPI or PSRAM master host controller IPs.
When coupled with the ACS xSPI/PSRAM PHY, the combined IPs are able to interact with SPI, Dual SPI, Quad SPI, Octal SPI, xSPI and 16-bit PSRAM devices at the 500Mb/s data rate per line (250MHz dual rate clock). This includes both HyperRAM and HyperFlash protocols. Both single and dual data rate modes are supported. The xSPI Master controller IP supports flash devices, whereas the xSPI/PSRAM controller has been designed to support SRAM types of devices using the same interface.
Features
- Supports for both the xSPI and PSRAM Master host controller IPs.
- Support 500Mbps per line along with the high speed xSPI modes > 50MHz.
- Supports a nominal 500 Mbit/s data rate, provided by the reference clock, as well as integer divisions of it
- Includes a DLL to facilitate clock and data strobe phase delays in units of 4*(clock_period/32). These offsets are required to generate the 90-degree phase offsets required of the xSPI/PSRAM protocol, as well as to adjust the return data sample timing to move it closer to the center of the data eye
- Supports On Chip Resistance calibration with retrigger option to re-calibrate the driver resistance if needed
- Option to manually force the calibration codes by bypassing the calibration block
- Provided a dedicated port to tap out the calibration code in the PHY level that can be used for calibrating external PHY’s technology resistor if needed
- Includes small two asynchronous FIFO one per data strobe for the purpose of accepting Strobe–clocked data
- Using the four chip select pins, the xSPI/PSRAM PHY can drive a shared bus with up to four memory chips present on it
- Supports extra pins, to include the interrupt detect (INTN), Error Correction Status (ECSN), write protect (WPN), reset (RESET N), and reset return (RSTO) wires used by some devices. These pins are optional in any implementation, and may not necessarily be used by all designs.
- Supports Push-Pull driver with different drive strength.
- Provided an optional weak pull-up resistor in all IOs to avoid the floating IO