Overview Arasan’s CAN-SEC Acceleration Engine Core implements the CAN-XL Protocol (CiA 610-1), CAN-XL Addon Part 1-Simple/Extercontent Indication (CiA 613-1), and CAN-XL Addon Part 2-Security (CiA 613- 2) Protocols.
Arasan’s CAN-SEC Acceleration Engine core is easy to integrate with the Host processor using AMBA-APB, AHB_Lite or AMBA-AXI standard interface. This highly configurable design supports programmable Interrupts, data and baud rates, acceptance filters & buffering schemes specific to the application.
Fig 1 Block Diagram of CAN-SEC with CAN-XL Controller
Table 1 Design Variants & Specifications they support
Verification
Arasan’s CAN-SEC Acceleration Engine Core has been rigorously verified and has been made production ready. It has been verified through extensive simulation and compliance check using multiple 3rd party Verification IPs. The Coverage report is available upon request. The CAN-SEC Acceleration Egine Core is verified during Synthesis, place and route and is ready for Plug Fests. This design can be ported to An ASIC or an FPGA design.
Support
The design core is delivered within 90 days from purchase. Thirty days of phone and email technical support is included. Optional maintenance support options are available for purchase.
Portable & Compatible Design
The RTL design can easily be ported to any ASIC or FPGA technologies. The top-level RTL is designed to easily accommodate ASIC level and FPGA level transceivers from various vendors. Design is compatible to any CAN-XL transceiver PHY that supports ISO-11898 from major ASIC and FPGA vendors.
Enhanced Safety
Arasan’s CAN-XL Core Controller is ISO-26262 ASIL-B ready. As an added option ISO-26262 ASIL-C can be provided. SRAM-ECC & End to end error detection & diagnostics, programmable Error threshold selection option.
Features
CAN-SEC Acceleration Engine Supports • CAN-XL Protocol (CiA 610-1) • CAN-XL Addon Part-1 (CiA 613-1) • CAN-XL Addon Part-2 Security (CiA-613-2) • AES-CMAC for Encryption • AES-GCM for Authenticated Encryption • Key Size-128,192 or 256 bits • Up to 256 CAN-SEC secure channels
Interfaces • Simple AMBA-APB, AMBA-AHB-Lite or Generic RAM like interfaces
Unique Benefits • Embedded DMA for reducing Gate count by moving Buffers outside the Controller • Easily configured to support AMBA-AXI4
Advanced Features • SDB-Software Defined Buffers, to support large external and small internal memories with minimum latency • Optimized design for short data frames to create latency advantage • Highly configurable design for data rate, baud-rate, interrupt sources and mix-bit options • Low software overhead, future-proof design
RAS Features • Advanced Error management unit prevents data loss during transmission and prevents message collisions • Designed to increase reliability, faster error reporting • Frame or Format error reporting is done on the receiver side in a timely manner • Supports debug, system maintenance and system optimization for Last error types, Arbitration lost position, error threshold indicators and others • Loopback mode for debug and self-testing during integration and system bring-up
Deliverables
Includes • System Verilog RTL Source Code • A simplified Testbench with simulation models to run initial set of tests after release • Synthesizable Netlist • Synthesis Scripts and exception lists • Timing Report • Protocol Compliance & Coverage Report • Sample Firmware with Drivers • Application Notes
Note*: ” License does not include the CAN Protocol License and CAN Trademarks”
