Arasan xSPI + eMMC Combo PHY IP

Overview
This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP. By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.

Diagram

xSPI+eMMC — Figure 1 Arasan’s xSPI/eMMC PHY Block Diagram

Features

• Dual-mode PHY supporting both xSPI and eMMC 5.1 protocols.
• JEDEC-compliant interfaces: JESD251 (xSPI) and eMMC 5.1.
• Shared I/O and analog front-end to reduce pin and area usage.
• Configurable protocol switching (software or hardware controlled).
• Built-in mux logic for interface selection and pad sharing.
• Suitable for boot with storage applications in embedded platforms.
• Max speed in eMMC5.1 Mode: HS400 supports with DDR clock 200MHz
• Max speed in xSPI Mode: xSPI-400 supports with DDR clock 200MHz

DLL and IOs features:

Analog DLL support for generating PVT independent clock delays
IO supports both push-pull transmitter and open-drain transmitter
Push-Pull transmitter supports different drive strengths (50ohm, 33ohm, 66ohm, 100ohm and 40ohm)
Differential receiver for better noise immunity

Test features:

DC-testing of IOs
BIST support
Analog DLL output phase measurement test

Deliverables

• GDSII
• CDL
• Physical verification reports
• Verilog simulation model
• Verilog Simulation environment
• IBIS model
• LEF
• LIB
• Gate level netlist with SDF timing for digital
• Scan inserted netlist for DFT
• User and Integration guide