xSPI PSRAM x16 Master IP core
Arasan Chip System’s PSRAM x16 master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports newer 16b PSRAM interfaces, in addition to such legacy interfaces as xSPI (JESD251), Octal SPI, QSPI, DSPI, and SPI, while offering both SDR and DDR modes
The PSRAM x16 master IP is built around two separate 8b data lanes. These can be operated either independently, or jointly for twice the throughput. This allows it to work with both newer PSRAM devices having two 8b data lanes, as well as legacy flash and PSRAM devices having only a single data lane.
The PSRAM x16 master IP is designed so that a user design may immediately access memory from a single slave device in SPI mode, or alternatively issue the commands necessary to switch to any other mode. Additionally, a DMA command may be issued to copy memory to or from the PSRAM device to anywhere else on the bus.
Features
JESD 251 compliant
- Protocols 1 & 2
Support HyperRAM, HyperFLASH, xCella, and xSPI
AP Memory 8-bit and 16-bit PSRAM support
Supports two 8b data lanes
- Doubles throughput (up to 1GB/s)
- Works with both 16b and non-16b memories
Multi SPI support
- Octal, Quad, Dual SPI
- DDR/DTR support
- Resets into SPI mode
- 24 or 32b addressing
- User selectable cmds
- XIP read support
- DS support in all modes
Full R/W support
AXI Memory Mapped
- Parameterized width
- Full & Narrow burst
- Max Bus Throughput
- Native WRAP support
AXI DMA master
- High Speed Bulk ops
- Parameterized width
- Full & Narrow burst
- Max Bus Throughput
AXI4-Lite Config Port
- Low level cmd access
- Configurable R/W cmds
Configurable clocking
- Device clock
- Integer clock divider
- Separate AXI clock
- (Optional) Clock gating
JESD SFDP capable