The SD 4.1 Device Controller IP core is used to implement SD cards that are connected to a Host processor over a standard SD bus. The SD 4.0 Device IP core is fully compliant with the SD specification. It supports the dual row pin memory cards with D0+/D0- and D1+/D1- pins for differential signaling.
It also supports SPI, SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full-speed SD data transfers are also supported to capacities up to 2TB. All version 4.0 features are supported including the UHS-II PHY, SDHS, mini-SD, embedded SD ATA standard function interface code, and extended 2.7-3.6V operating voltages. The SD 4.1 Device Controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required.
The core supports asynchronous interrupts to the Host processor for improved performance. It supports suspend/resume operation for improved performance. The controller integrates a scatter-gather DMA engine automating data transfers between the SD card and system memory.
The SD 4.1 Device Controller IP core is available with several system bus interfaces including AHB, AXI, OCP, Avalon, BVCI, SPI and custom buses.