The SDIO 3.0 Device IP core is used to implement SDIO cards that are connected to a Host processor over a standard SD bus. The flexible architecture of the SDIO Device IP core is targeted to develop a range of portable, low-power cards such as the WiFi (802.11), GPS, WiMAX, UWB, LTE.
The SDIO 3.0 Device IP core is fully compliant with the SD Specification Part E1 SDIO 3.0. It supports SPI, SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full-speed SD data transfers are also supported. All version 3.0 features are supported including the UHS-I, SDHS, miniSDIO, embedded SDIO ATA standard function interface code, and operating voltages 2.7-3.6V or 1.7-1.95V . In applications with an AHB interface, the SDIO 3.0 Device is controlled by an ARM processor.
The SDIO 3.0 Device controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required. The core supports asynchronous interrupts to the Host processor for improved performance. It supports suspend/resume operation for improved performance.
The controller integrates a scatter gather DMA engine automating data transfers between the SDIO card and system memory. The SDIO 3.0 Device Controller is available with many system bus interfaces including AHB, AXI, OCP, Avalon, BVCI, SPI and custom buses. The wide selection of interfaces enables the core to integrate effectively SOC designs today.