eMMC 4.51 is the latest specification released by JEDEC and is designed to meet the requirements for secure yet flexible program code and data storage for consumer electronic products. With its low-pin count, high bandwidth and multiple boot mechanisms eMMC 4.51 greatly simplify system design for new products.
Arasan’s eMMC 4.51 Device Controller IP is compliant with the latest eMMC specification. The controller provides a bandwidth of up to 1.6Gb/s in 200 MHz modes. A NAND Flash memory device can be connected to the eMMC memory controller. In such an implementation, the controller’s AHB interface provides a channel for data transfers between the memory controller and a NAND flash controller (also available from Arasan).
The eMMC 4.51 Device Controller supports the newer eMMC functions such as E2MMC devices, extended partitioning, command packing, context IDs, data tags and dynamic device capacity. The memory controller operates at a maximum frequency of 200 MHz. The eMMC interface supports MMC 1-bit, 4-bit, and 8-bit modes. eMMC supports power-on booting without the upper level of software driver which simplifies system design. The controller shields the host system from the functional differences among various NAND flash architectures (such as MLC). The explicit sleep mode allows the host to instruct the controller to directly enter a low power sleep mode. The controller supports block lengths or sector sizes of 512, 1024, 2048 and 4096 bytes.
Compliant to JEDEC JESD84-B45 eMMC 4.51 spec
Packed commands for faster processing
Supports cache control mechanism
Supports eMMC4.51 Security Protocol Commands
Peak bandwidth of 1.6Gbps with 200 MHz clock
Includes context IDs and data tagsv
Dynamic device capacity tracks mapped out bad blocks
Supports 1-, 4-, or 8-bit data bus
Supports all commands described in the eMMC specification
Compatible with previous eMMC standards
Supports Sector address allowing host to access high capacity over 2GB
Supports Extended Partition Management features with enhanced storage options
Security features such as Discard, Sanitize, Replay Protected Memory Block (RPMB)
Sleep mode for power saving
CRC7 for command and CRC16 for data integrity
Write protection (Power-on, Temporary, and Permanent), and password features
Supports native sector sizes of 512-bytes or 4K-bytes
AHB Complies to AMBA specification version 2.0.
Supports incremental burst transfers in DMA mode
Supports register transfer in non-DMA mode
Supports retry and split
The Arasan eMMC 4.51 Device Controller IP Core utilizes a flexible system bus architecture that can support AXI, AHB, OCP or any custom system interface needed for existing SoC development. The IP core includes RTL code, test scripts and a test environment for complete design verification.
Fully compliant core
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