The Arasan I3C Device IP Core Implements Device functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is used for various sensors in the mobile/automotive system where an I3C Master transfers data and controls information between itself and various sensor devices. The I3C Device Controller IP Core can be easily integrated into the Sensor/Device devices with minimal gate count.
The I3C Device controller is highly configurable (synthesis time) to provide an optimal solution based on the Device’s requirements. This includes, acting as a legacy I2C device, Support for Dynamic Address Assignment, HDR (any of the three defined HDR Modes) and a configurable FIFO for data transfers. In addition, optional I3C Device functions like Interrupt generation, Hot-Join request generation and advanced Device with secondary master capabilities can be configured for more complex Devices. Also, the I3C Device Controller IP provides direct signalling to connect to the IO Buffers (SCL and SDA). Please note that the User needs to provide appropriate IO buffers to meet the I3C specification.
The I3C Device controller implements support for legacy I2C Device functionality, Open-drain and Push-pull operation of I3C Interface, and Dynamic Addressing support. The I3C Device Controller supports the required SDR mode with Clock frequency of up to 12.5 MHz and optionally any or all of the three HDR modes as defined by the I3C Specification. The included 16 byte FIFO (Configurable) is used to handle data transfers between IP and the Application.
Arasan has participated in multiple MIPI I3C Interop Workshops to ensure compliance of it’s I3C Master IP, Device IP, I3C Software and HDK