MIPI | CSI
Arasan MIPI CSI-2 Receiver IP Core
The Arasan MIPI CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface Receiver, between a peripheral device (Camera module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Receiver IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.
CSI-2 RX v1.2 is compliant to MIPI CSI-2_specification_v1-2 and supports D-PHY v1.1.
CSI-2 RX v1.3 is compliant to MIPI CSI-2 v1.3 specification and supports DPHY v1.1 or v1.2 and the new MIPI C-PHY v1.1.
Arasan offers the C-PHY in a combination configuration that supports both C-PHY interfaces and D-PHY interfaces. Our implementation makes efficient use of the high frequency signally pins for a minimal overhead to support both physical interfaces.
The Datasheet for CSI-2 RX v1.3 is available on request
Diagram
Features
- Use of either D-PHY/C-PHY by user configuration
- Different Configuration allowed for multiple use cases
- 4-Lane/8-Lane D-PHY / 3-Lane C-PHY
- Lane Configurability depending on the bandwidth requirements of the application, up to 8-lanes for DPHY and up to 4-lanes for C-PHY
- High Speed (HS) receiver rates of 182Mbps to 5714Mbps per lane with C-PHY interface
- High Speed (HS) receiver rates of 40Mbps to 2500Mbps per lane with D-PHY interface
- Supports for Ultra Low Power Mode (ULPS)
- Single (or) Optional Multi-Pixel mode interface to ISP. The multi-pixel mode is used in high bandwidth requirement applications to lower the ISP clock frequency requirement.
- Optional Pixel Level Interface to ISP with HSYNC, VSYNC, DATA and DATA VALID
- Streams the received pixels onto eight data channels(customizable) based on the channel configurability from ISP
- Separate data channel for the short generic packets
- Support for all packet level errors, Protocol Decoding Level errors
- Support for cut-though (or) store and forward mode. Cut-through mode makes use of shallow Memory for memory critical applications.
- Optional support for Compressed data formats
- Optional support for different error counting
- Pixel formats supported
- RAW data type – RAW8, RAW10, RAW12, RAW14
- YUV data type – YUV422-8bit, YUV422-10bit
- RGB data type – RGB888, RGB666, RGB565, RGB555, RGB444
- All user Defined data types / JPEG
- Generic 8-bit long packet data types
- Host interface for register configuration and monitoring,
- Used for programming both CSI-2 and PHY related registers. Reserved address space [0x00 – 0x0F] for the PHY related registers.
- Optional support for the AHB/APB/Microcontroller Interface
Deliverables
- Verilog HDL of the IP Core
- Synthesis scripts
- Verification environment
- User guides for design and verification
Benefits
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Product quality proven with silicon
- Premier direct support from Arasan IP core designers
