ARASAN’S VESA DSC V1.2 DECODER

VESA DSC Decoder

Overview

VESA introduced the first Display Stream Compression (DSC) standard in 2014. The DSC 1.1 has been incorporated into the VESA Embedded DisplayPort (eDP) and MIPI® DSI embedded mobile interface standards. The latest VESA Display Compression-M (VDC-M) standard has also been adopted into the MIPI DSI standard. For mobile applications, DSC 1.1 and VDC-M mainly serve to reduce the video interface data rate, which reduces system power, prolongs battery life, and reduces interconnects to enable sleeker designs. For external display interfaces, DSC 1.2b extends resolution across existing connectors and cables, enabling 8K video and legacy support from the same connection.

Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.

Features

Compliant with the VESA DSC 1.2a and 1.2b standards
Performs decoding
Supports 8/10/12/14/16 bpc
- 4:4:4 RGB, 8, 10, and 12 bpc
- 4:4:4 YCbCr, 8, 10, and 12 bpc
- 4:2:2 YCbCr 8, 10, and 12 bpc
- 4:2:0 YCbCr, 8, 10, and 12 bpc
- Any mode, 14 and 16 bpc
The decoder algorithm is optimized for hardware implementations at 3 pixels/clock (6 pixels/clock for Native 4:2:2 or 4:2:0 mode)
Supports MMAP, BP, MPP and ICH

Programmable display resolutions

Key Features

Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
Low gate count and low latency implementation
Three clock domains
Stream and APB clocks operate the applicable interfaces
Independent decoder clock runs the core functions
Fully compliant with the VESA Display Stream Compression(DSC) 1.2 standard
Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers
Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core
Completely pipelined; can be stalled as necessary to properly manage input and output rates

Deliverables

Verilog HDL of the IP Core
Synthesis scripts
Verification environment
User guides for design and verification

Benefits

Fully compliant to VESA standards
Small footprint
Code validated with HAL and 0-in-CDC
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers