Arasan’s VESA DSC v1.2 decoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel in RGB or YCbCr format (4:4:4 or 4:2:2). The DSC Encoder core is industry-standard in its integration of host setup and control, data input, and visual output. Arasan’s VESA DSC decoder IP is seamlessly integrated with Arasan’s DSI Rx IP. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP
Host 32-bit AMBA Peripheral Bus 4 (APB) slave interface for programming and control. All internal configuration and status registers are accessible from the slave APB interface.
AXI4-Stream Protocol interface supports the transfer of encoded data to the core at 2 or 4 bytes per clock cycle.
Parallel streaming interface with end of-line and top-of-frame indicators.