Arasan’s Total IPTM Solution for MIPI Display Serial Interface (DSI-2SM) with VESA DSC IP provides both device and host functionality along with VESA DSC encoder and decoder functionalities that are defined in the latest MIPI DSI and VESA DSC specifications. This IP provides an end-to-end Total IPTM solution for the leading-edge displays enabling reduction in data transmission bandwidth for upto 4k or 8k displays with higher refresh rates and visually lossless compression. The DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D/C-PHY analog IP and VESA DSC components. Arasan’s DSI solutions are MIPI standards compliant and are designed to accelerate integration, lower risk, and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
VESA DSC Encoder/Decoder
The encoder/decoder core compresses and decompresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel in RGB or YCbCr format (4:4:4 or 4:2:2). The DSC Encoder/ Decoder core is industry-standard in its integration of host setup and control, data input, and visual output.
Arasan’s MIPI DSI-2℠ Device Controller
Display modules consist of display driver logic driving display signals onto a display device or panel. On the display driver side, Arasan’s DSI-2 Device Controller provides the DBI Interface for Types 1 to 3 display modules and the DPI Interface for Types 2 to 4 displays. Initial configuration of this IP can be done through programmed IO over the AHB bus; however, other bus interfaces can be provided upon request.
Arasan’s MIPI DSI-2℠ Host Controller
The Arasan DSI Host Controller IP is designed to provide MIPI DSI 2 v1.1 compliant high speed serial connectivity for mobile application processors using 1 to 4 D-PHY’s lane /1-3 C-PHYs lane depending on bandwidth needs. Serial connectivity to the display module’s DSI device is implemented using 1 to 4 D lane/1-3 C-PHYs lane (also available from Arasan), depending on display bandwidth needs. This IP connects to the D-PHY’s/C-PHY’s through the PPI interface.
On the application processor side, Arasan’s DSI Host Controller provides the choice of DPI or DBI Interface to a graphics controller. A DBI interface provides downstream support of Types 1 to 3 display modules, and the DPI Interface is needed for Types 2 to 4 displays.
Initial configuration of this IP can be done through programmed IO over the AHB bus; however, other bus interfaces can be provided upon request.
Arasan’s MIPI D/C-PHY Physical interface
The Arasan D/C-PHY IP core is fully compliant to the D/C-PHY specification. It supports the Display Serial Interface (DSI) protocols. It is a universal PHY that can be configured as a transmitter, receiver, or transceiver. The D/C-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. The Arasan D/C-PHY provides a point-to-point connection between host and device that comply with a relevant MIPI® standard. A typical configuration consists of a clock lane and 1-4 data lanes for D-PHY and 1-3 data lanes for C-PHY. The host is primarily the source of data, and the device is usually the sink of data. The D/C-PHY lanes can be configured for unidirectional or bidirectional lane operation, originating at the host, and terminating at the device. The D-PHY link supports a high speed (HS) mode for fast data traffic and a low power (LP) mode for control transactions. In HS mode, the low swing differential signal can support data transfers from 80 Mbps to 2.5 Gbps for DPHY and 5.7 Gbps for CPHY. In LP mode all wires operate as a single ended line capable of supporting 10 Mbps asynchronous data communications. The Arasan D/C-PHY IP core implements the PPI interface recommended by the MIPI® working groups to easily interface to the required protocols.