eMMC Host Controller IP

The eMMC Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies: eMMC 4.51 SD 3.0 SDIO 3.0 The eMMC Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware […]

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CSI-2 V2.1 Transmit

The Arasan MIPI CSI-2 Transmitter IP Core functions as a MIPI Camera Serial Interface between a peripheral device (display module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Transmitter IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions. Pixel Data received from over the […]

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CSI-2 V2.1 Receiver

The Arasan MIPI CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface Receiver, between a peripheral device (Camera module) and a host processor (baseband, application engine). The Arasan MIPI CSI-2 Receiver IP provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions. Arasan MIPI CSI-2 Receiver is […]

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MPHY V4.1 G4 & G3

MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY configuration (LINK) consists of a minimum of two unidirectional lanes along with associated lane management logic. Each of the M-PHY lanes consists of a lane module (M-TX) that communicates to a corresponding module (M-RX) […]

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I3C

Overview The main purpose of MIPI I3C is to standardize sensor communication, reduce the number of physical pins used in sensor system integration and support low-power, high-speed and other critical features supported by I2C and SPI. Features MIPI I3C V1.0 compliant Up to 12.5Mhz (with push-pull I/O) Single (SDR) and Hi-speed (HDR) messaging APB/AHB Target […]

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I3C HDK

The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box. The HDK contains I3C Master and Slave FPGA Boards programmed with Arasan’s I3C Master & Slave IP respectively, I3C software stacks and reference schematics. The HDK will also […]

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UFS 3.0 Host-AES

Arasan’s Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host processing and nonvolatile eXecute-In-Place (XIP) or mass storage memory devices. Mobile phones, UMPC, DSC, PMP are some of the typical applications for UFS Host Controller IP. Majority of these applications require mass storage […]

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CPHY HDK

The C-PHY HDK is build using Arasan’s TSMC 28nm C-PHY ASIC. Future generations of the HDK will use Arasan’s TSMC 12nm C-PHY ASIC. The HDK supports C-PHY v1.1 with speeds of up to 2.5 GHz. This HDK enables customers to prototype their CPHY based projects using Arasan’s MIPI CSI or DSI IP controller cores and […]

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UFS 3.0 Device

UFS 3.0 is the next specification update pending from JEDEC. Arasan will offer UFS 3.0 compatible Host and Device Controllers late Q2 2017 to select customers. Key Differences between UFS 3.0 and UFS 2.1 are: Multiple RPMB regions with unique auth key, registers an logical address Mandatory support for Gear3 5.8Gbps (M-PHY v3.x) Mandatory support […]

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