Arasan Chip Systems, a leading provider of semiconductor IP for automobile SoCs, today announced that its MIPI DSI-2 Rx IP has achieved ISO26262 ASIL-B automotive certification SAN JOSE, Calif., Aug. 26, 2025 /PRNewswire/ — Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its ISO26262 ASIL-B Certified […]
Arasan’s xSPI/eMMC5.1 PHY: Unified Dual-Mode Physical Layer IP
Introduction As SoCs evolve to support a growing range of memory interfaces, designers are faced with the challenge of balancing integration complexity, pin efficiency, and performance scalability. Traditionally, implementing both xSPI (JESD251) for boot and eMMC 5.1 for high-speed storage required separate PHYs, leading to increased silicon area, power consumption, and I/O overhead. Arasan’s xSPI/eMMC5.1 […]
Arasan’s xSPI/eMMC5.1 PHY: A Unified Solution for Next-Gen SoCs
System-on-Chip (SoC) designers face a recurring challenge: integrating multiple memory interfaces without bloating area, pin count, or design complexity. Arasan’s xSPI/eMMC5.1 PHY directly addresses this by combining two widely used memory standards—xSPI (JESD251) and eMMC 5.1—into a single PHY IP. This dual-mode integration enables both boot functionality (via xSPI) and high-speed storage (via eMMC 5.1), […]
One PHY, Two Protocols: Arasan’s xSPI / eMMC Combo PHY IP
Modern SoCs need to do more with less — less silicon, fewer pins, lower power, faster integration. When it comes to memory, this challenge often means balancing the need for fast boot from NOR flash with high-speed storage from eMMC. Traditionally, these functions required two separate PHYs, adding area, complexity, and cost. Arasan’s xSPI / […]
Arasan Announces the industries first MIPI SWI3S Manager IP and Peripheral Controller IP
Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the industry’s first SWI3S Manager IP and Peripheral IP Cores SAN JOSE, Calif., Aug. 6, 2025 /PRNewswire/ — Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of the industry’s first MIPI […]
Arasan’s SoundWire‑I3S™ IP: Empowering the Next Era of Embedded Audio
As audio technologies advance across mobile, automotive, and edge AI applications, system designers are demanding simpler, smarter, and scalable interfaces. Enter SoundWire‑I3S™—the next-generation MIPI standard that unifies audio, control, and power management over a minimal two-wire connection. At the forefront of this evolution is Arasan Chip Systems, delivering a robust, silicon-proven SoundWire‑I3S IP solution engineered […]
Breaking the Silence: What Is SoundWire‑I3S and Why It Matters
In the world of smart audio, silence is no longer golden—it’s strategic. The way devices communicate audio and control data is evolving rapidly, and at the heart of that evolution is a new standard quietly transforming embedded systems: SoundWire‑I3S™. Developed by the MIPI Alliance, SoundWire‑I3S is the successor to the widely used SoundWire® protocol. It […]
Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY
Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its Embedded USB2 (eUSB2) IP Core. SAN JOSE, July 9, 2025 /PRNewswire/ — Arasan Chip Systems, a leading provider of semiconductor IP for mobile and automobile SoCs, today announced the immediate availability of its Total IP for […]
How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
In the race to build smaller, smarter, and more efficient devices, audio system-on-chips (SoCs) must meet increasingly demanding requirements: high fidelity, low latency, low power, and seamless integration. The SoundWire PHY from Arasan Chip Systems is engineered to meet these challenges and elevate your next audio SoC design from standard to standout. 1. Low Power […]
Unlocking Ethernet Flexibility with MII-Based PHY Support
Learn how MII-based PHY support enhances Ethernet flexibility, compatibility, and future connectivity. Explore real-world applications and use cases.