Arasan Chip Systems has announced the MIPI LLI (low-latency interface) controller IP along with a matching type-1 M-PHY. The LLI is a chip-to-chip link layer interconnect protocol that allows low-latency cache refills from the DRAM associated with a companion chip. This removes the need for two separate sets of DRAMs, claims the company. A combined LLI controller and M-PHY type-1 layer can be configured for host buses such as a advanced high-performance bus, an advanced extensible interface and open core protocol, and to meet bandwidth and latency requirements across multiple traffic classes. Using up to six lanes of M-PHYs, the controller IP offers up to 17Gbit/s bandwidth in each direction, with only one clock domain crossing in the LLI controller.