Arasan Chip Systems Adds DigRF(SM) 3G IP to Its MIPI(R) IP Portfolio

SAN JOSE, Calif., Jan. 12, 2010 (GLOBE NEWSWIRE) — Arasan Chip Systems, Inc. ("Arasan"), a leading provider of Total Intellectual Property (IP) Core Solutions, announced the release of its DigRF(SM) 3G IP core that enables the integration of 2.5G/3G cellular chipsets into mobile platforms. Arasan's IP enables Baseband chips to "plug-and-play" with a wide supply of DigRF(SM) compliant chipsets that implement the latest cellular standards.

The rapid evolution of cellular standards poses a challenge for Baseband processor designers in being able to support these new standards. DigRF(SM) is a standard, scalable interface between Baseband chips and RF chipsets enabling a platform approach to solve this challenge. Arasan's DigRF(SM) 3G IP enables Baseband processors to interface with chipsets supporting either dual mode of operation — 3GPP 3G/2,5G or single mode 2.5G (UMTS/EGPRS). Arasan's IP enables Baseband and RF chipsets to be connected via a standard interface independent of the RF implementation. The interface minimizes the pin count and power while reducing data transfer errors.

"The large variety of form-factors of mobile phones places unique demands on the layout of components such as RF chipsets," said Prakash Kamath, Vice-President of Engineering at Arasan. "By integrating Arasan's DigRF(SM) IP core, mobile chipset designers can support multiple types of diversity, improving radio performance while easing system-level layout of these sensitive components."

"Mobile platform developers need a scalable radio interface to keep up with evolving RF standards," said Somnath Viswanath, Product Marketing Manager at Arasan. "These platform designers can now support multiple generations of RF chipsets by integrating Arasan's DigRF(SM) IP core."

Arasan's DigRF(SM) IP core enables multiple form-factor solutions with varying types of diversity for better performance. The interface consists of two differential signal pairs one each for transmit and receive. The frame format and electrical interface are designed to eliminate interface signal errors — resulting in very low protocol overhead for data transfers.

Arasan provides a "Total IP Solution" for its DigRF(SM) 3G IP consisting of RTL source code for IP cores, Verification IP and documentation all backed by world-class customer support.