Modern SoCs need to do more with less — less silicon, fewer pins, lower power, faster integration. When it comes to memory, this challenge often means balancing the need for fast boot from NOR flash with high-speed storage from eMMC. Traditionally, these functions required two separate PHYs, adding area, complexity, and cost.
Arasan’s xSPI / eMMC Combo PHY IP changes that equation.
What It Is
This dual-mode PHY IP integrates both:
- xSPI (Expanded Serial Peripheral Interface) compliant with JEDEC JESD251
- eMMC 5.1 compliant with JEDEC eMMC standards
…into a single, unified physical layer.
By sharing the same I/O pads and analog front-end, the Combo PHY enables two distinct protocols to coexist in one IP block, making SoC design leaner and more flexible.
Why It Matters
With Arasan’s combo PHY:
- One IP does the work of two → smaller silicon footprint
- Fewer pins → simpler packaging and reduced cost
- Built-in protocol switching → hardware or software-controlled muxing between xSPI and eMMC
- Seamless integration → no need for external switching logic
It’s a smarter way to design SoCs that need both boot flash and high-speed storage.
Performance at a Glance
- eMMC 5.1 Mode
- HS400 with DDR clock at 200MHz
- xSPI Mode
- xSPI-400 with DDR clock at 200MHz
The Combo PHY is tuned for reliable boot performance and sustained high-speed data transfer, delivering the best of both worlds.
Built for Robustness
The PHY includes a rich set of features to ensure reliability and ease of bring-up:
- Analog DLL for PVT-independent clock delays
- Configurable I/O with push-pull and open-drain modes
- Selectable drive strengths (50Ω, 33Ω, 66Ω, 100Ω, 40Ω)
- Differential receiver for improved noise immunity
And for test/debug:
- DC I/O testing
- Built-in Self-Test (BIST)
- DLL output phase measurement
- DC scan support
Where It Fits
The xSPI / eMMC Combo PHY is designed for embedded platforms where boot and storage functions must coexist efficiently:
- Mobile SoCs
- Automotive ECUs
- Consumer electronics
- Industrial & IoT controllers
Anywhere an SoC needs fast boot + high-speed storage, this combo PHY brings performance and efficiency together.
Conclusion
Arasan’s xSPI / eMMC Combo PHY IP is not just about saving pins or area — it’s about giving SoC designers the flexibility to support multiple memory standards without compromise. With dual-mode operation, JEDEC compliance, and robust testability, this IP is a ready-made solution for next-gen SoCs that demand more from less.
