SAN JOSE, Calif., Sept. 30, 2009 (GLOBE NEWSWIRE) — Arasan Chip Systems, Inc. ("Arasan"), a leading provider of Intellectual Property (IP) Cores, announced the availability of the MIPI(R) D-PHY IP compliant with the v1.0 standard released September 22, 2009 by the MIPI Alliance. With this release, Arasan continues to demonstrate its commitment to its Strategic Mobile Initiative by being the first to deliver fully verified MIPI IP comprising of software stacks, controllers and the D-PHY.
ABI Research in New York said that smart phones shipments should reach 203 million in 2009, a 17 percent jump over the 171 million sold in 2008. To accommodate the increasing amount of multimedia content and design complexity that smart phones are accessing, new chip designs for these handsets will benefit from the high-speed MIPI bus interfaces on board. Arasan's new MIPI D-PHY will ease the incorporation of these interfaces.
Arasan's MIPI D-PHY IP is a low-pin count, high-speed, low power physical layer interface common to camera (CSI), display (DSI) and UniPro(SM) MIPI protocols. Migrating to this serial interface simplifies component layout while saving valuable PCB real estate and power in mobile systems. By leveraging Arasan's D-PHY IP, mobile phone developers can rapidly introduce innovative feature-packed phones by connecting application processors with the appropriate MIPI compliant chipsets.
"The D-PHY is a critical element at the front end of Camera and Display MIPI Alliance interface," said Joel Huloux, Chairman of the Board, MIPI Alliance, Inc. "Having an IP core readily available to implement the newest version 1.0 of the specification released on September 22, will ensure a fast time to market for system on chip designs containing MIPI Alliance interfaces standards."
"Arasan has been at the forefront of enabling MIPI adoption by releasing MIPI IPs coinciding with the formal spec," said Rich Timpa, Executive Vice-President at Arasan. "By using Arasan's Total MIPI IP Solutions, SoC designers can meet their aggressive time to market goals while mitigating risk to ensure first time success."
"Arasan's D-PHY IP leverages a Digital Assisted Analog approach to ensure interoperability and minimize the risk of porting to different fabs and process nodes, which is the life blood of an IP solution company," said Ignatius Bezzam, Senior Director of the Analog Mixed Signal Division at Arasan.
Arasan's D-PHY IP core is implemented on standard CMOS processes, which eases the integration effort for this IP. It is available on leading process nodes and foundries.
Arasan continues to be the only IP provider with a complete portfolio of MIPI IPs. Its MIPI D-PHY IP is the result of the close interaction between Arasan and the MIPI alliance to ensure rigorous compliance with the specification. Arasan thoroughly verifies the interoperability of its software stack, controller and PHY in order to reduce SoC design risk while speeding up the integration of MIPI interfaces.
As part of its Total IP Solution approach, Arasan offers a one stop shop for MIPI RTL IP cores (UniPro, SLIMbus(R), CSI, DSI, HSI), vIPs, software stacks, analyzers, validation platforms and complete documentation to assist SoC teams in succeeding with their designs.