CMOS design engineer with strong analog design expertise as well as mixed-signal design capabilities. Positions are available in San Jose, CA and in Bangalore, India.
- Development of high speed SERDES for MIPI, D-PHY and M-PHY applications, with an extension to other projects such as; USHII, USB 2.0 and USB 3.0.
- Architecture definition, schematic generation, layout generation, blocks assembly, verification, and lab evaluation.
- Provide technical interface to customers, milestone and deliveries.
- Responsible for technical leadership and mentoring of junior design engineers.
- Will be required to seek and encourage new approaches and architectures for Market advantage.
- Ensure on time delivery and quality of PHY IP and active involvement in problem solving & implementing opportunities for improvement.
- Interfacing / interacting with other development teams.