The Future of Chip to Chip Communication

Sam Beal
Internet Marketing Manager

In Internet network infrastructure data transport using TCP/IP or RTP is implemented at layers 2 & 1 with egress packet conversion and VCSELs. Packet processors for ingress (“header shreaders”) manage flow control for QoS (and provide a good place to foil net neutrality). There are no “buses” between Internet routers – just optical fiber carrying wavelenth-dense multiplexing at bandwidths exceeding 1Tbps. The same trend will come to dominate in chip-to-chip communications. The IC industry has embraced the OSI model used select chip to chip data classes. For example: PCIexpress, originally created to move data between the CPU and the GPU, has evolved with Gen3 to become a standard mass storage interface. For mobile applications, JEDEC UFS provides an interface to NAND Flash storage. And the new MIPI LLI standard provides low latency, low power, chip-to-chip interfaces. This is a death knell for high pin count packages. Using buses to achieve bandwidth between ICs in a system will evolve to specialized high-speed Ser/Des IO. Specialized IP that interfaces to internal standard SoC buses, like AXI, AHB, OCP, etc. will packetize, serialize/deserialize, and de-packetize data using increasingly higher transport speeds while reducing IC power and area. Ultimately this function will be virtually absorbed into the I/O pad. The reduction in pin count will simplify package and PCB routing and signal integrity, yield higher system performance and low cost. Written by