Validate a USB core with the HVP

SD3.0 HVP Picture


Designers planning to use software IP cores  always have to ask themselves, how are they going to validate the IP cores both before and after they are implemented in an SoC. Their software colleagues often ask; “How can we start software development sooner?”   The answers to these questions usually involves building an FPGA-based prototype but this can be time-consuming and overkill when the target function is not the entire SoC. Arasan provides its IP customers with ready-made Hardware Validation Platforms (HVPs),  based on a Linux platform, that greatly simplifies the process.   HVPs containing software, FPGA-instantiated IP and a Linux-based interface are available for many IP types including UFS, UniPro, SD/SDIO/eMMC and RFFE. Arasan has been shipping USB 2.0  IP cores since 1996 which now include Host, Device, Hub OTG, PHY and HSIC PHY.  Here’s a short video which shows how an  Arasan HVP platform has been set up with USB 2.0 Device IP to act as a mass storage device. [jwplayer config=”Out-of-the-box” mediaid=”6671″]