MIPI D-PHY is the physical interface for CSI-2 and DSI providing up to 4.5Gbps per lane of bandwidth. The latest board approved specification is D-PHY v2.0 released March 8, 2016.
This specification is primarily intended to define a solution for a bit-data rate range of:
- 80 to 1500 Mbps per Lane without de-skew calibration,
- up to 2500 Mbps with de-skew calibration,
- and up to 4500 Mbps with equalization.
When the DUT implementation supports a data rate greater than 1500 Mbps, it shall also support de-skew capability. When a PHY implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available.
Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 2.0. It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a Universal PHY that can be configured as a transmitter, receiver or transceiver. The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital (PPI) interface to control the I/O functions.