VESA DSC V1.2 Encoder

Overview

Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10, 12, 14 or 16 bits per pixel in RGB or YCbCr format (4:4:4 or 4:2:2). The DSC Encoder core is industry-standard in its integration of host setup and control, data input, and visual output. Arasan’s VESA DSC Encoder IP is seamlessly integrated with Arasan’s DSI Tx IP. Arasan’s expertise is backed by our unique silicon-proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.

Arasan’s VESA DSC Encoder Core

Host

Host 32-bit AMBA Peripheral Bus 4 (APB) slave interface for programming and control. All internal configuration and status registers are accessible from the slave APB interface.

Input

Parallel streaming interface with VSync and HSync support for image framing.

Output

AXI4-Stream Protocol interface is implemented to support the transfer of encoded data.

Key Features

Capable of decoding up to 4K video at 30fps in FPGA and 8K video at 30fps in ASIC applications
Low gate count and low latency implementation
Three clock domains
Stream and APB clocks operate the applicable interfaces
Independent decoder clock runs the core functions
Fully compliant with the VESA DSC 1.2 standard
Uses synchronous design techniques and a technology abstraction layer for internal SRAM buffers
Allows for migration from FPGA or FPGA prototype to ASIC with no functional changes to the core
Completely pipelined; can be stalled as necessary to properly manage input and output rates

Deliverables

Verilog HDL of the IP Core
Synthesis scripts
Verification environment
User guides for design and verification

Benefits

Fully compliant to VESA standards
Small footprint
Code validated with HAL and 0-in-CDC
Functionality ensured with comprehensive verification
Product quality proven with silicon
Premier direct support from Arasan IP core designers