Mipi CSI 2 V1.2 to V2.1

Introduction

About CSI

The MIPI®Alliance the Camera Serial Interface (CSI-2) dates back to November 2005 and was in widespread use in consumer devices by 2009. CSI-2 V1.1 was approved in January 2013. CSI-2 v1.2 was released in September 2014. The updated version, CSI-2 v1.3 (covered in this document) was released in February 2015.

Demand for increasingly higher image resolutions is pushing the bandwidth capacity of existing host processor-to-camera sensor interfaces. Common parallel interfaces are difficult to expand, require many interconnects and consume relatively large amounts of power. Emerging serial interfaces address many of the shortcomings of parallel interfaces while introducing their own problems. Incompatible, proprietary interfaces prevent devices from different manufacturers from working together. This can raise system costs and reduce system reliability by requiring “hacks” to force the devices to interoperate. The lack of a clear industry standard can slow innovation and inhibit new product market entry.

CSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, costeffective interface that supports a wide range of imaging solutions for mobile devices.

Arasan’s Contribution to MIPI

Arasan has been a member of MIPI for over ten years. We are active participants in a number of working groups. We work closely with other member customers to ensure compliant implementation of standards-based IP.

Arasan’s Total IP Solution

Arasan provides a Total IP Solution, which encompasses all aspects of IP development and integration, including analog and digital IP cores, verification IP, software stacks & drivers, and hardware validation platforms. Benefits of Total IP Solution:

• Seamless integration from PHY to Software
• Assured compliance across all components
• Single point of support
• Easiest acquisition process (one licensing source)
• Lowest overall cost including cost of integration
• Lowest risk for fast time to market

Figure 1: Arasan’s Total IP Solution

CSI-2 v1.3 Transmitter IP

Overview

Arasan Chip Systems is a leading SOC IP provider of a complete suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, software stacks and drivers, protocol analyzers, hardware platforms for software development and compliance testing, and optional customization services.

The MIPI compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to a smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources, and lower power and EMI.

This document describes the Arasan IP Core that functions as a MIPI CSI-2 Transmitter, which typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link to a CSI2 Receiver in the applications processor. The Arasan CSI-2 combo IP is MIPI-compliant and provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.

Features

• Compliant with the following MIPI specifications:
  • mipi_CSI-2_specification_v1-3
  • mipi_CSI-2_specification_v1-2
  • mipi_D-PHY_specification_v1-2
  • mipi_C-PHY_specification_v1-0
• CSI-2 Combo Transmitter Core features:
  • Use of either D-PHY/C-PHY by user configuration
  • Lane Configurability depending on the bandwidth requirements of the application, up to 8-lanes for DPHY and up to 4-lanes for C-PHY
  • Connectivity to DPHY/CPHY through MIPI PPI Interface
  • High Speed (HS) transmit rates of 182Mbps to 5714Mbps per lane with C-PHY interface
  • High Speed (HS) transmit rates of 40Mbps to 2500Mbps per lane with D-PHY interface
  • Support for Ultra Low Power Mode (ULPS)
  • Support for Continuous and Non-Continuous Clock Mode
• Pixel formats supported
  • RAW data type
  • YUV data type
  • RGB data type
  • All user Defined data types / JPEG
  • Generic 8-bit long packet data types
• Supports Data Type Interleaving
• Supports Virtual Channel Interleaving
• Pixel Level Input Interface for Image Sensor
• Supports Header and Payload Checksum
• Configurable for two mode of operation
  • Store and Forward Mode – Stores the full pixel packet before forwarding.
  • Cut through Mode – Initiates the HS transmission to D/CPHY as soon as the pixel information is received. Makes use of very shallow memory.
• Supports Multi Pixel Mode – Multiple Pixels per clock to bring down the sensor clock
  frequency to support higher resolution applications
• PPI Data Lane swapping as per user configuration
• Optional support for Compressed data formats

• • Host interface for register configuration and monitoring,
    • Used for programming both CSI-2 and PHY related registers. Reserved address space
      [0x00 – 0x0F] for the PHY related registers.
    • Optional support for the AHB/APB/Microcontroller Interface

Architecture

Functional Description

The Arasan CSI-2 Transmitter IP is designed to provide MIPI CSI-2 v1-2/ CSI-2 v1-3 compliant high speed serial connectivity for camera modules in mobile platforms. Serial connectivity between this IP to the mobile applications processor’s CSI-2 Receiver is implemented using 1 to 8 D-PHY Lanes (or) 1 to 6 C-PHY lanes, depending on camera sensor resolutions and the resulting bandwidth needs. This IP connects to the D-PHY/CPHY through the PPI interface. The PPI interface of the IP is compliant to MIPI mipi_D-PHY_specification_v1-2/mipi_C-PHY_specification_v1-0. The usage of PHY’s is selected by simple programming based on the use case.

Initial configuration of this IP and its associated D-PHY/C-PHY can be done through programmed IO over an AHB/APB bus. However, another bus interface can be provided upon request.

Pixel Data received from over the Camera Sensor Bus is packed into bytes by the Transmitter IP. The packing of the pixel into bytes follows the CSI-2 spec and based on the pixel format support. This IP calculated and appends an ECC/CRC value to a short packet (or) to the header of a long packet. Selection of ECC/CRC to the header is done based on the PHY connected. For the payload of a long packet carrying pixel data, this IP calculates its CRC value and appends it to the packet as a Packet Footer (PF). The packet is buffered in a FIFO and sent to one or more D-PHY/C-PHY depending on the lane distribution scheme set by the camera sensor/user.

Functional Block Diagram

Figure 2: Combo Transmitter Functional Block Diagram

Configuration-64-Bit Internal Data Bus

The IP can be programmed to use with following configuration, when the internal data bus is 64-bit.

PHY Layer –DPHY

Note: The frequency of sensor clock can vary as long as the FIFO does not underflow and depends on the pixel mode/clock configuration.

Figure 3: Combo Transmitter Usage with 4-Lane D-PHY Version 1.2

Figure 4: Combo-Transmitter Usage with 8 Lane D-PHY Version-1.2

PHY Layer–CPHY

Figure 5: Combo Transmitter Usage with 3-Lane C-PHY

Functional Block Diagram Description

AHB Target Interface

This module connects the CSI-2 Transmitter core to external AHB processor. The user can configure the different application-specific attributes through set of registers. The user can program the lanes, pixel mode and also can get status information’s like FIFO status, ULPS status etc. This can be used to program both CSI-2 and PHY related registers.

Packet Sensor Interface

This module interfaces to external sensor. The module provides a handshake mechanism to accept the long pixel data packet and the synchronization packets like Frame Start (FS), Line Start (LS), Line End (LE) and Frame End (FE). This also controls the data flow from the external sensor interface to the CSI-2 Combo Transmitter Controller.

Pixel to Byte Convertor

This module converts the received pixel information to byte as per the CSI-2 specification. The respective pixel to byte convertor will get enabled based on the received data type. This module converts the received pixel information and sync packet information to 64-bit and forwards it to external memory. This module also takes care of compression of pixel information.

FIFO

This is library specific dual Port (or) Two Port RAM, which is instantiated outside the CSI-2 IP. This is used as temporary storage buffer. The size of the buffer would vary based on the application. In cut-through mode application, which makes use of very shallow memory, this FIFO could be replaced with the register based memory. However, for store and forward architectures the size of the memory varies with the size of the resolution required. Usually for store and forward the size of the FIFO should be 2 * MAX Line size required.

Packet Reader

This module keeps track the number of packet to be processed. In cut-through mode applications, initiates the read as per the required threshold for the respective data format. Whereas in store and forward mechanism, this module waits for the complete packet to be stored in the FIFO before forwarding it to the low level protocol layer for further processing.

Low Level Protocol

This module based on the packet format received calculates the ECC/CRC for header and frames the packet header. For the received payload, calculates the CRC and appends it to the packet as packet footer.

Lane distribution Layer

This module takes care of the bytes/word distribution on to different D-PHY/C-PHY data lanes based on the user lane configuration. This will provides the PPI interface for the D-PHY/C-PHY. The clock lane layer manages the Clocks Lane PPI interface for D-PHY/C-PHY

CSI-2 Combo Transmitter Pin Diagram

Figure 6: CSI-2 Combo Transmitter Pinout

SOC Level Integration

IP Deliverables

• • • Verilog HDL of the IP core
    • User guide
    • Synthesis scripts
    • Lint report
    • CDC report
    • Verilog test suite
    • Gate count estimation available upon request

Verification Environment

Figure 7: Verification Environment of CSI-2 Combo Transmitter IP

CSI-2 v1.3 Receiver IP

Overview

Arasan Chip Systems is a leading System on Chip (SoC) Intellectual Property (IP) provider of a complete suite of Mobile Industry Processor Interface (MIPI) compliant IP solutions, which consists of IP cores, verification IP, software stacks and drivers, protocol analyzers, hardware platforms(HVP’s) for software development and compliance testing and optional customization services.

The Mobile Connectivity (MIPI) compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms. This leads to smaller footprint, greater interoperability between mobile IP, chips and devices from diverse sources and lower power and Electro-Magnetic Interface (EMI).

This document describes the Arasan IP Core that functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Camera module) and a host processor (baseband, application engine). The CSI-2 Combo Receiver IP communicates over a D-PHY (or) C-PHY serial link to image processing block, part of the application engine. The Arasan CSI-2 combo IP is MIPI compliance and provides a standard, scalable, low-power, high-speed interface that supports a wide range of higher image resolutions.

Features

• • • Compliant with the following MIPI specifications
      • mipi_CSI-2_specification_v1-3
      • mipi_CSI-2_specification_v1-2
      • mipi_D-PHY_specification_v1-2
      • mipi_C-PHY_specification_v1-0
    • CSI-2 Combo Receiver Core features:
      • Use of either D-PHY/C-PHY by user configuration
      • Different Configuration allowed for multiple use cases, 4-Lane/8-Lane D-PHY / 3-Lane C-PHY
      • Lane Configurability depending on the bandwidth requirements of the application, up to 8-lanes for DPHY and up to 4-lanes for C-PHY
      • High Speed (HS) receiver rates of 182Mbps to 5714Mbps per lane with C-PHY interface
      • High Speed (HS) receiver rates of 40Mbps to 2500Mbps per lane with D-PHY interface
      • Supports for Ultra Low Power Mode (ULPS)
      • Single (or) Optional Multi-Pixel mode interface to ISP. The multi-pixel mode is used in high bandwidth requirement applications to lower the ISP clock frequency requirement.
      • Optional Pixel Level Interface to ISP with HSYNC, VSYNC, DATA and DATA VALID
      • Streams the received pixels onto eight data channels(customizable) based on the channel
        configurability from ISP
      • Separate data channel for the short generic packets
      • Support for all packet level errors, Protocol Decoding Level errors
      • Support for cut-though (or) store and forward mode. Cut-through mode makes use of shallow Memory for memory critical applications.
      • Optional support for Compressed data formats
      • Optional support for different error counting
    • Pixel formats supported
      • RAW data type – RAW8, RAW10, RAW12, RAW14
      • YUV data type – YUV422-8bit, YUV422-10bit
      • RGB data type – RGB888, RGB666, RGB565, RGB555, RGB444
      • All user Defined data types / JPEG
      • Generic 8-bit long packet data types
    • Host interface for register configuration and monitoring
      • Used for programming both CSI-2 and PHY related registers. Reserved address space [0x00 –0x0F] for the PHY related registers.
      • Optional support for the AHB/APB/Microcontroller Interface

Architecture

Functional Description

The Arasan CSI-2 Receiver IP is designed to provide MIPI CSI-2 v1-2/ CSI-2 v1-3 compliant high speed serial connectivity for application processors to corresponding camera modules in mobile platforms. Serial connectivity between this IP and an external camera module’s CSI-2 transmitter is implemented using 1 to 8 D-PHY Lanes (or) 1 to 6 C-PHY lanes, depending on camera sensor resolutions and the application bandwidth needs. This IP connects to the D-PHY/CPHY through the PPI interface. The PPI interface of the IP is compliant to MIPI mipi_D-PHY_specification_v1 2/mipi_C-PHY_specification_v1-0. The usage of PHY’s is selected by simple programming based on the use case.

Initial configuration of this IP and its associated D-PHY/C-PHY can be done through programmed IO over an AHB/APB bus. However, another bus interface can be provided upon request.

This IP performs the data lane merging of pixel data received on the PPI interface. It performs CRC and ECC checks to ensure the integrity of the packet payload and the header. Based on the PHY connected, lanes are merged accordingly and respective checks will be performed automatically. As per the application setting, IP either forwards (or) drops the erroneous packets. All forwarded packet payloads are then converted from byte to respective pixel format and output to an Image Signal Processor of the applications processor’s graphics sub-system. A simple Pixel Level Interface is used to forward the pixel information. All PHY level errors, packet-level errors and decoding level errors are communicated to the HOST.

Functional Block Diagram

Figure 8: Functional Block Diagram

Configuration – 64-Bit Internal Data Bus

The IP can be programmed to use with the following configuration when the internal data bus is 64-bit.

PHY Layer – DPHY

The CSI-2 Combo Receiver IP can be used to configure a number of lanes from 1 to 8.

Note: – The frequency of ISP clock can vary as long as the FIFO does not overflow and depends on the pixel mode/clock configuration.

Figure 9: Combo Receiver Usage with 4 Lane D-PHY V 1.2

Figure 10: Combo Receiver Usage with 8 Lane D-PHY V 1.2

PHY Layer – C-PHY

Figure 11: CSI-2 Combo Receiver Usage with 3 Lane C-PHY V 1.2

unctional Block Diagram Description

AHB Target Interface

This module connects the CSI-2 Receiver core to an external AHB processor. The user can configure the different application-specific attributes through a set of registers. The user can program the lanes, pixel mode and also can get status information like PHY level information, Packet level error information, etc. This can be used to program both CSI-2 and PHY related registers.

Lane Merger

The CSI-2 Receiver is lane-scalable for increased performance. The number of data lanes may be chosen depending on the bandwidth requirement of the application. This module collects the bytes from the lanes programmed and merges them together into a recombined data stream that restores the original stream sequence. On merging the bytes, forward the stream to the LLP layer for further processing. This module also handles the inter lane skew for the C-PHY application.

Low Level Protocol Unit

This module determines if the received packet is of type short (or) long. For long packets, a CRC check is performed on the payload by comparing a calculated checksum on the payload with the checksum received with packet. If connected PHY is D-PHY, an ECC check is performed on the header, single-bit errors are corrected and 2-bit errors are detected. If connected PHY is C-PHY, a CRC is performed on header received. This module also checks for all type of protocol and decoding level errors. This module takes care of interrupt generation for the critical decisions from the application. Depending on the application/use case settings, this block decides whether to forward (or) drop the erroneous packets.

FIFO

The FIFO module is used to synchronize the data flow from the LLP clock domain to ISP’s clock domain. The FIFO size is configurable based on the user requirement. The FIFO size is based on the mode of operation chosen for the application. The Receiver IP adopts cut-through (or) store and forward functional modes. The cut-through requires a very shallow memory and for the store and forward, memory size varies with the use case. For application, which makes use of 1 to 8 lanes DPHY and 1 to 3- lanes C-PHY, the width of the FIFO would be 64-bit. However, for other configurations (6-lane C-PHY) the FIFO width required would be 96-bit. Depending on the IP configuration, the internal data bus will get change

Byte2Pixel Unit

This module unpacks the received byte stream to pixel format with respect to the received data type.
This module takes care of enabling the respective pixel unit.

To ensure compatibility with camera modules that support data compression on RAW data types,
this unit implements the two prediction and the six decompression schemes specified in the CSI-2 standard. This feature is optional and is register programmable.

Image Processor Unit

This module further processes the received pixel information and packs them into multiple pixels based on the user configuration. For high-resolution applications, the requirement of higher ISP clock can be reduced by adopting the multi-pixel (more than one pixel per clock) mode operation. It also forwards control information like data type, frame number, line number, virtual channel number and packet boundary signals, namely frame start, line start, line end and frame end.

MIPI Virtual Channel Interface

This is an optional interface. This module forwards the received pixel information to configured data channel. This module interfaces to eight pixel data channels. The decision on which data channel, the received pixel to be forwarded is controlled by the external ISP. The external ISP provides 8 set of control information (each set will have virtual channel and data type). This module along with pixel data also generates HYSNC and VSYNC signals for the respective virtual channel.

CSI-2 Combo Receiver Pin Diagram

Figure 12: CSI-2 Receiver Combo PIN Diagram

SOC Level Integration

IP Deliverables

• • • Verilog HDL of the IP Core
    • User guide
    • Synthesis scripts
    • Link report
    • CDC report
    • Verilog test suite
    • Gate count estimates available upon request

Verification Environment

• • • A comprehensive suite of simulation tests for ease of SoC integration
    • Verification components and test files provided
    • Verification environment and test suite well documented

Figure 13: Verification Environment of CSI-2 Receiver IP