Arasan - About MIPI

About the MIPI Alliance

The Mobile Industry Processor Interface (MIPI) Alliance is a collaboration of mobile industryleaders with the objective to define and promote open standards forinterfaces to mobile application processors. Through these open standards,the MIPI Alliance intends to speed deployment of new services to mobileusers by establishing specifications for standard hardware and software interfacesto mobile application processors and encouraging the adoption of thosestandards throughout the industry value chain. The MIPI Alliance isintended to complement existing standards bodies with a focus onmicroprocessors, peripherals and software interfaces.

About DSI Host and Display Cores

The Arasan MIPI DSI Host and Display IP cores are complaint with the MIPI DSI Specification Version 1.0. They provide the interface between a graphic display module, such as a host processor, to a peripheral display, through a physical layer device such as the D-PHY. They are built on existing MIPI Alliance standards by adopting pixel formats and the command set specified in the DPI-2, DBI-2, and DCS standards. A DSI interface performs the same functions as interfaces based on DBI-2 and DPI-2 standards or similar parallel display interfaces. It sends pixels or commands to the peripheral, and can read back status or pixel information from the peripheral. DSI serializes all pixel data, command and events that, in traditional or legacy interfaces, are normally conveyed to and from the peripheral on a parallel data bus with additional control signals. The protocol layer appends packet protocol information and headers, and then sends the complete bytes through the Lane Management Layer to the PHY. Packets are serialized by the PHY and sent across the serial link. The receiver side of a DSI link performs the converse of the transmitter side, decomposing the packet into parallel data, signal events and commands. If there are multiple lanes, the Lane Management Layer distributes bytes to separate PHY’s (one PHY per lane). Packet protocols and formats are independent of the number of lanes used.

The Arasan DSI IP Host and Display cores are an RTL design in Verilog that can be implemented on an ASIC, or FPGA.

About the CSI-2 Rx and Tx Cores

The Arasan MIPI CSI-2 IP is available as Receiver or Transmitter IP. The operation of the Receiver and Transmitter IP is compliant with the Camera Serial Interface-2 Version 1.00 specification and has been silicon validated. The cores interface between a digital imaging module such as a host processor or an image sensor peripheral such as a camera, through a physical layer device such as a D-PHY. The IP cores have an AHB or PCI interface that allows a processor to convert data received by the CSI-2 Receiver to pixel format, JPEG, or MPEG format.

The Receiver has a lane management unit and a “depacketiser” unit to handle 1 to 4 data lanes. A CCI (Camera Control Interface Bus) master handles the control of the camera serial interface. The CCI slave at the CSI-2 transmitter peripheral receives control signals sent by the CCI master of the CSI-2 receiver. All higher layer functions are handled including lane management, protocol management, byte to pixel conversions, picture viewing applications, image format conversions, and other applications as specified by the MIPI CSI specification,

The Transmitter has a lane management and a “packetiser” unit to handle 1 to 4 data lanes. A CCI (Camera Control Interface Bus) slave is connected to a CSI-2 receiver. All CCI registers are memory mapped to the AHB or PCI host processor to support different CSI-2 receiver devices.

The Arasan MIPI CSI-2 Receiver and Transmitter IP include RTL code, test scripts and a test environment for full simulation verifications. They along with and Arasan D-PHY IP core provide a complete solution for mobile digital camera applications with data transfer rate up to 4 Gbits/s.

About the SLIMbus Core

The Arasan MIPI SLIMbus IP is available as Host Controller IP or Device Controller IP. SLIMbus is a 2-wire multi-drop TDM bus that allows a wide variety of audio and digital data devices to be connected. Examples include microphone, speaker, vibration elements, and low speed Bluetooth devices.

The Arasan SLIMbus Host Controller IP is combines the Interface, Manager, and Framer functionalities. The Manager performs the configuration and controlling functions by sending control messages via the Shared Message Channel. It also responsible for assigning logical addresses to any device that is authorized to communicate via the bus. The Framer that is responsible for driving the clock signal and generating SLIMbus frames. The clock gear logic is also available that allows the clock rate to be changed to reduce the bus power consumption. The SLIMbus Host Controller IP supports up to 64 input or output ports. All data transport profiles such as the isochronous, and extended asynchronous data transmissions are supported.

The SLIMbus Device IP core consists of an Interface Device and one or more Generic Devices. The Interface Device provides bus management services for the component in which it resides. The Interface Device controls the frame layer and monitors message protocols implemented by the component. The Interface Device also manages component reset so that a component can properly sequence its devices. In addition, the Interface Device reports information about the status of the component. The Generic Device provides single or multiple interfaces to external applications through the I2S, SPI, I2C, UART, parallel, or other custom interfaces. External applications such as a MEMS microphone can be connected to a selected I/O. The Generic Device supports all transport protocols including isochronous and extended asynchronous transfers. Up to 64 I/O ports per component can be supported with one or more generic devices.

The SLIMbus Host and Device Controller IP Cores include RTL code, test scripts and a test environment for full simulation verifications.

	MIPI Main Page About the MIPI Alliance The Mobile Industry Processor Interface (MIPI) Alliance is a collaboration of mobile industryleaders with the objective to define and promote open standards forinterfaces to mobile application processors. Through these open standards,the MIPI Alliance intends to speed deployment of new services to mobileusers by establishing specifications for standard hardware and software interfacesto mobile application processors and encouraging the adoption of thosestandards throughout the industry value chain. The MIPI Alliance isintended to complement existing standards bodies with a focus onmicroprocessors, peripherals and software interfaces. About DSI Host and Display Cores The Arasan MIPI DSI Host and Display IP cores are complaint with the MIPI DSI Specification Version 1.0. They provide the interface between a graphic display module, such as a host processor, to a peripheral display, through a physical layer device such as the D-PHY. They are built on existing MIPI Alliance standards by adopting pixel formats and the command set specified in the DPI-2, DBI-2, and DCS standards. A DSI interface performs the same functions as interfaces based on DBI-2 and DPI-2 standards or similar parallel display interfaces. It sends pixels or commands to the peripheral, and can read back status or pixel information from the peripheral. DSI serializes all pixel data, command and events that, in traditional or legacy interfaces, are normally conveyed to and from the peripheral on a parallel data bus with additional control signals. The protocol layer appends packet protocol information and headers, and then sends the complete bytes through the Lane Management Layer to the PHY. Packets are serialized by the PHY and sent across the serial link. The receiver side of a DSI link performs the converse of the transmitter side, decomposing the packet into parallel data, signal events and commands. If there are multiple lanes, the Lane Management Layer distributes bytes to separate PHY’s (one PHY per lane). Packet protocols and formats are independent of the number of lanes used. The Arasan DSI IP Host and Display cores are an RTL design in Verilog that can be implemented on an ASIC, or FPGA. About the CSI-2 Rx and Tx Cores The Arasan MIPI CSI-2 IP is available as Receiver or Transmitter IP. The operation of the Receiver and Transmitter IP is compliant with the Camera Serial Interface-2 Version 1.00 specification and has been silicon validated. The cores interface between a digital imaging module such as a host processor or an image sensor peripheral such as a camera, through a physical layer device such as a D-PHY. The IP cores have an AHB or PCI interface that allows a processor to convert data received by the CSI-2 Receiver to pixel format, JPEG, or MPEG format. The Receiver has a lane management unit and a “depacketiser” unit to handle 1 to 4 data lanes. A CCI (Camera Control Interface Bus) master handles the control of the camera serial interface. The CCI slave at the CSI-2 transmitter peripheral receives control signals sent by the CCI master of the CSI-2 receiver. All higher layer functions are handled including lane management, protocol management, byte to pixel conversions, picture viewing applications, image format conversions, and other applications as specified by the MIPI CSI specification, The Transmitter has a lane management and a “packetiser” unit to handle 1 to 4 data lanes. A CCI (Camera Control Interface Bus) slave is connected to a CSI-2 receiver. All CCI registers are memory mapped to the AHB or PCI host processor to support different CSI-2 receiver devices. The Arasan MIPI CSI-2 Receiver and Transmitter IP include RTL code, test scripts and a test environment for full simulation verifications. They along with and Arasan D-PHY IP core provide a complete solution for mobile digital camera applications with data transfer rate up to 4 Gbits/s. About the SLIMbus Core The Arasan MIPI SLIMbus IP is available as Host Controller IP or Device Controller IP. SLIMbus is a 2-wire multi-drop TDM bus that allows a wide variety of audio and digital data devices to be connected. Examples include microphone, speaker, vibration elements, and low speed Bluetooth devices. The Arasan SLIMbus Host Controller IP is combines the Interface, Manager, and Framer functionalities. The Manager performs the configuration and controlling functions by sending control messages via the Shared Message Channel. It also responsible for assigning logical addresses to any device that is authorized to communicate via the bus. The Framer that is responsible for driving the clock signal and generating SLIMbus frames. The clock gear logic is also available that allows the clock rate to be changed to reduce the bus power consumption. The SLIMbus Host Controller IP supports up to 64 input or output ports. All data transport profiles such as the isochronous, and extended asynchronous data transmissions are supported. The SLIMbus Device IP core consists of an Interface Device and one or more Generic Devices. The Interface Device provides bus management services for the component in which it resides. The Interface Device controls the frame layer and monitors message protocols implemented by the component. The Interface Device also manages component reset so that a component can properly sequence its devices. In addition, the Interface Device reports information about the status of the component. The Generic Device provides single or multiple interfaces to external applications through the I2S, SPI, I2C, UART, parallel, or other custom interfaces. External applications such as a MEMS microphone can be connected to a selected I/O. The Generic Device supports all transport protocols including isochronous and extended asynchronous transfers. Up to 64 I/O ports per component can be supported with one or more generic devices. The SLIMbus Host and Device Controller IP Cores include RTL code, test scripts and a test environment for full simulation verifications.
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