SECURE DIGITAL SOLUTIONS
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The Secure Digital (SD) bus transfers data between the host computer and the peripheral devices using either a 1-bit data bus or 4-bit data bus. The peripheral devices can be either memories or I/O devices or a combination of both. The data transfer is done synchronously and the data bus width can be changed dynamically by the host computer. SD bus provides a maximum data transfer rate of 200 Megabits/sec. The host computer acts as a master and provides SD slots for connecting multiple slaves (peripheral devices). The peripheral devices can be connected or disconnected without shutting down the host computer.
The SD bus has a clock signal from the host computer to the peripheral devices. Each SD slot of the host computer has bidirectional command/response signal line and also 4 bidirectional data lines. The peripheral devices can operate at a low speed (SD clock is 0-400 KHz) or at a high speed (0-50 MHz). Low speed is suitable for applications such as modems, bar-code scanners and GPS receivers. The peripheral device containing both memory and I/O need to be a full speed device. The speed of an I/O peripheral device is made known to the host through a bit setting in the card capability register present in the Common I/O Area (CIA) of the device.
The host issues appropriate command tokens to an I/O or memory peripheral device. Device send response tokens against the command tokens. Command tokens issued from host can contain specific addresses to access the register or memory locations inside the device. Data can be either the part of command/response tokens or they can flow in separate data blocks between host and device. Application specific commands are possible to help the implementation of security features in the SD memory devices. Device can have up to seven I/O functions along with the memory and function number present in the commands helps the host to access the different functions.
Typical data transfer between the host and the I/O device takes place on device interruption to the host. The device can signal interrupt using a data signal line and the host will issue the data transfer command to the device.
The CIA within the device help the host to control the device by enabling/disabling the interrupts and I/O functions. Also the CIA contains device specific information such as the maximum supported frequency and block size.
The SD bus protocol provides ways to control the data transfer rate between the host and the device. The device can indicate a 'Busy' situation through a data signal line during a write operation from the host. The host can ask the device to 'wait' by signaling through a data line during the read operation from the device.
Either because of the above mentioned data transfer rate mismatch between host and device or because of a built in priority, the host can suspend the data transfer to a given I/O function and can start transferring data to another I/O function.
Arasan offers the SDIO Card Controller IP Core and the standard SD Host Controller IP Core.