CEATA SOLUTIONS
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CE-ATA is based on the MMC electrical interface, using an optimized subset of the ATA command set to improve performance for multimedia applications in handheld and consumer electronic devices.
CE-ATA was publicly announced in September 2004 at the Intel Developer Forum by a group of industry-leading companies specializing in various market segments. Discussions among these companies revealed a common question regarding the necessity of addressing storage in consumer electronics. Industry leaders were presented with the burgeoning demand for cost-effective solutions to enable the adoption of higher capacity digital storage afforded by disk drives into host systems such as handheld and consumer electronic devices. As such, it was realized that a collaborative effort to define a comprehensive solution for the storage interface would best serve our respective markets.
Arasan's CE-ATA Host Controller IP conforms to CE-ATA Digital Protocol revision 1.1RC, with support for CE-ATA Digital Protocol commands (CMD60 / CMD61). The CE-ATA interface allows for lower pin count, better power utilization, voltages tailored to battery-based applications, and more efficient command protocol.
Through industry adoption of CE-ATA, consumers will have access to a greater variety of innovative products including digital music players, PDAs, personal video players, cellular handsets, GPS navigation systems, automotive devices, and various new and emerging applications. CE-ATA-based products will offer compatibility and interoperability with other CE-ATA devices to further enable the concept of mobility and "plug and play".
PATA SOLUTIONS
The Advanced Technology Attachment (ATA) is a proven standard to interconnect hard disk drives (HDD), solid state drives (SSD), CD/DVD-ROM and other media to a host system. The parallel interface of the ATA is also referred to as PATA and enables multiple disk drives to be connected over a flexible cable in a cost effective manner.
Arasan’s ATA IP core supports the ATA/ATAPI-6 standard. This standard extends the Logical Block Addressing to 48 bits enabling the host to interface with larger capacity drives. The controller directly interfaces to an ATA/ATAPI on the device side and supports a native AHB target bus interface on the application side for easy integration into an SoC.