Arasan Chip Systems has a long history of PCI IP development starting with its first PCI controller released in 1997. PCIe Gen1 and now Gen2 are a de facto standard interconnect for high-performance computing and embedded products such as NICs, storage cards and graphic accelerators. Arasan’s proven PCIe cores reduces the risk and shortens the design cycle for SoCs that integrate a PCIe interface.
- Arasan’s PCIe Gen2 IP listed in PCI-SIG integrator list
- PCIe 2.1 cores are backward compatible with PCIe 2.0, 1.1 specification
- PCIe IP supports flexible lane configurations
- Customizable host interface for optimum performance
- Total IP solution for PCIe includes RTL source code, synthesis scripts, test environment and detailed documentation
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